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Interactive teaching materials by Han Tian.
Software Optimization for Intelligent Computing
Chapter 5 · GPU Architecture and Computational Optimization
01Interactive demo · Matrix multiplication
Compare naive multiplication, register tiling, and shared-memory plus register tiling. Follow matrix accesses, data reuse, and output accumulation step by step.
- HBM and on-chip storage
- Tiling and reuse
- Aᵀ execution view
02Interactive demo · Attention
Select actual tiles within the full Q, Kᵀ, and V matrices. Follow their elements from HBM to on-chip GPU storage, through local computation and online Softmax, and back to the matching output tiles in O.
- Standard Attention baseline
- Online Softmax
- FA1 / FA2 work partitioning
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